This invention relates to a semiconductor memory device, and more particularly to a technology which is effective when applied to a static RAM of large capacity.
As stated in "Nikkei Electronics" published on Sept. 26, 1983, pp. 125-139, static RAMs have increasingly been enlarged in capacity and enhanced in speed. First, the arrangement of a static RAM will be briefly explained.
FIG. 1 shows an example of the whole arrangement of a semiconductor memory device which was developed by the inventors in the course of developing the present invention. The memory device 100 shown in the figure has a memory mat 10 in which a large number of memory cells M are arrayed in the shape of a matrix consisting of rows and columns, an X decoder/driver 20 and a Y decoder 30 which serve to select the memory cell within the memory mat 10 on the basis of address data A.sub.i, and so forth.
The X decoder/driver 20 decodes the lower (or upper) bit data of the address data A.sub.i, to prepare alternative select signals X.sub.0 -X.sub.n. The select signals X.sub.0 -X.sub.n are applied to word lines W which are laid in the row direction of the memory mat 10.
The Y decoder 30 decodes the upper (or lower) bit data of the address data A.sub.i, to prepare alternative select signals Y.sub.0 -Y.sub.n. The select signals Y.sub.0 -Y.sub.n are applied to a Y select switch bank (column switch bank) 40. The Y select switch bank 40 operates to select any of complementary data line pairs D and D, each pair of complementary data lines being laid in the column direction of the memory mat 10.
In the above way, the memory cells M within the memory mat 10 are respectively selected in the row direction and the column direction. The memory cell M, which is connected in the place of intersection between the row and the column selected on the basis of the address data A.sub.i, is connected to common data lines L.sub.1 and L.sub.2 through the selected complementary data line pair D and D as well as the Y select switch bank 40. The change of potentials appearing on the common data lines L.sub.1 and L.sub.2 is detected by a read sense circuit 50, and the detected result becomes the read output D.sub.out of stored data. Data D.sub.in is written into the memory mat 10 by the data write circuit 55. This data write circuit includes a data input buffer DIB, a data input intermediate amplifier DIIA, MOS transistors m.sub.1 and m.sub.2 (which elements are shown, for example, in FIG. 9) and a bias circuit 60 (shown in various forms in FIGS. 2, 3, 5, 6, 7 and 9). The data write circuit 55 receives the write enable signals WE(WE) and the chip select signals CS(CS). These signals can be applied to the bias circuit 60 as shown in FIG. 9. The details of connection of these signals to bias circuit 60, as well as details of the data write circuit 55, are omitted from FIGS. 2, 3, 5, 6 and 7 for simplicity.
FIG. 2 shows part of the internal circuitry of the memory device illustrated in FIG. 1, which part has been similarly developed by the inventors in the course of developing the present invention. As shown in the figure, each of the paired complementary data lines D and D has one end thereof connected to a common power source V.sub.CC through a MOS field effect transistor for pull-up m.sub.11 and has the other end thereof connected to the common data line L.sub.1 or L.sub.2 through a Y select switch (column switch) S.sub.1 or S.sub.2 included in the Y switch bank 40. Accordingly, the stored information written in the selected memory cell M can be read out in such a way that the change of the potentials complementarily appearing on the common data lines L.sub.1 and L.sub.2 is detected by the read sense circuit 50. The select switches S.sub.1 and S.sub.2 in the Y select switch bank 40 are respectively constructed using MOS field effect transistors.
The Y select switches S.sub.1 and S.sub.2 are all rendered OFF (non-conductive) in a non-selected mode, that is, when no valid address data signals are input. At this time, the common data lines L.sub.1 and L.sub.2 are connected to none of the complementary data line pairs D, D. On this occasion, there arises the condition that the common data lines L.sub.1 and L.sub.2 fall into floating states and that their potentials are not fixed.
When the common data lines L.sub.1 and L.sub.2 are in the floating states in the non-selected mode charges which have been stored in capacitors parasitic thereto are discharged, and the potentials of these common data lines L.sub.1 and L.sub.2 are reduced to low potentials (for example, potentials close to the ground potential). Therefore, when any memory cell is subsequently selected to read out information stored therein, a long time is required before the potentials of the common data lines rise up to a level at which the sense circuit for detecting the potential change of the complementary data line pair operates stably. Accordingly, a long access time is involved.
The inventors have therefore provided an arrangement wherein, as illustrated in FIG. 2, a bias circuit 60 is disposed, and the common data lines L.sub.1 and L.sub.2 are always supplied with fixed potentials (potentials close to those at which the sense circuit operates stably), thereby to shorten the access time.
The bias circuit 60 devised by the inventors as shown in FIG. 2 is such that impedance elements Z.sub.1, Z.sub.2, Z.sub.3 and Z.sub.4 formed of MOS field effect transistors are employed for assembling two sets of voltage divider circuits (Z.sub.1 and Z.sub.3, and Z.sub.2 and Z.sub.4), and that voltages at respective voltage division points are applied to the common data lines L.sub.1 and L.sub.2. The two sets of voltage divider circuits (Z.sub.1 and Z.sub.3, and Z.sub.2 and Z.sub.4) are respectively connected across the common power source V.sub.CC and the ground potential, and they supply the corresponding common data lines L.sub.1 and L.sub.2 with the voltages obtained through the resistance voltage division of the voltage across the common power source V.sub.CC and the ground potential. Thus, the common data lines L.sub.1 and L.sub.2 are prevented from falling into the electrically floating states and are biased at fixed potentials. The MOS field effect transistors as the impedance elements Z.sub.1 -Z.sub.4 are respectively controlled to turn ON so as to have predetermined equivalent resistances (impedances) by fixed control voltages V.sub.S1 and V.sub.S2.
Meanwhile, the inventors have conducted research from the viewpoints of lowering the power consumption and enhancing the operating speed of a static RAM, and, as a result, have developed a technology wherein a static RAM is constructed using both bipolar transistors and MOS transistors. An outline of this technology will now be discussed. In an address circuit, a timing circuit, etc. within a semiconductor memory, an output transistor for charging and discharging a signal line of long distance and an output transistor of large fan-out are formed of bipolar transistors, while logic circuits for executing logic processes, for example, the processes of inversion, non-inversion, NAND and NOR are formed of CMOS circuits. The logic circuit formed of the CMOS circuit is of low power consumption, and the output signal of this logic circuit is transmitted to the signal line of long distance through the bipolar output transistor of low output impedance. Since the output signal is delivered to the signal line by the use of the bipolar output transistor having the low output impedance, the dependence of a signal propagation delay time upon the stray capacitance of the signal line can be lessened, this function realizing the semiconductor memory of low power consumption and high speed.
On the basis of the above technology of the high speed and low power consumption SRAM employing the bipolar-CMOS hybrid technology, the inventors further studied the enhancement of access time. As a result, it has been revealed better for shortening the access time to lower the potential of a common data line and to render the impedance of the common data line (or the amplitude of a signal on the common data line) smaller.
That is, it has been found that when the impedances of the common data lines L.sub.1 and L.sub.2 are rendered as small as possible, time constants which are determined by capacitances C.sub.S1 and C.sub.S2 parasitic to the respective common data lines L.sub.1 and L.sub.2 and the impedances of these common data lines can be reduced, so the signal transfer speeds of the common data lines can be enhanced.
It has also been found that when the potentials of the common data lines are high, a differential pair of transistors Q.sub.1 and Q.sub.2 constituting the sense amplifier SA 50 as shown in FIG. 2 come to have high base potentials and become close to saturation because of constant collector voltages. This forms one factor in lowering the signal transfer speeds.
When it is intended as a countermeasure to reduce the impedances of the common data lines and to lower the potentials thereof by the use of the common data line potential generating circuit 60 shown in FIG. 2, the ON resistances of the MOSFETs Z.sub.1, Z.sub.2, Z.sub.3 and Z.sub.4 as the impedance elements need to be made small in resistance value. It has been found, however, that when the ON resistances (equivalent impedances) of the MOSFETs Z.sub.1 -Z.sub.4 within the common data line biasing circuit 60 are rendered small for the purpose of lowering the impedances of the common data lines L.sub.1 and L.sub.2, a through current I.sub.x flowing through the MOSFETs Z.sub.1 -Z.sub.4 in the non-selected mode (i.e. a current flowing in the direction of an arrow in the figure) increases. Therefore, power consumption in this portion attributed to direct current will be increased
That is, it has been revealed by the inventors in studying the arrangement of FIG. 2 which they developed that the contradictory problem occurs in which, when the ON resistances of the MOSFETs within the common data line biasing circuit 60 are reduced for enhancing the operating speed, the power consumption in the non-selected mode increases.